Analysis & Synthesis report for DE0_NANO
Wed Aug 15 18:18:44 2018
Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 Patches 0.01we SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Registers Removed During Synthesis
  9. General Register Statistics
 10. Port Connectivity Checks: "VGA_DRIVER:driver"
 11. Port Connectivity Checks: "Dual_Port_RAM_M9K:mem"
 12. Post-Synthesis Netlist Statistics for Top Partition
 13. Elapsed Time Per Partition
 14. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, the Altera Quartus II License Agreement,
the Altera MegaCore Function License Agreement, or other 
applicable license agreement, including, without limitation, 
that your use is for the sole purpose of programming logic 
devices manufactured by Altera and sold by Altera or its 
authorized distributors.  Please refer to the applicable 
agreement for further details.



+------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                                   ;
+------------------------------------+-----------------------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Wed Aug 15 18:18:44 2018                     ;
; Quartus II 64-Bit Version          ; 15.0.0 Build 145 04/22/2015 Patches 0.01we SJ Web Edition ;
; Revision Name                      ; DE0_NANO                                                  ;
; Top-level Entity Name              ; DE0_NANO                                                  ;
; Family                             ; Cyclone IV E                                              ;
; Total logic elements               ; 0                                                         ;
;     Total combinational functions  ; 0                                                         ;
;     Dedicated logic registers      ; 0                                                         ;
; Total registers                    ; 0                                                         ;
; Total pins                         ; 71                                                        ;
; Total virtual pins                 ; 0                                                         ;
; Total memory bits                  ; 0                                                         ;
; Embedded Multiplier 9-bit elements ; 0                                                         ;
; Total PLLs                         ; 0                                                         ;
+------------------------------------+-----------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; EP4CE22F17C6       ;                    ;
; Top-level entity name                                                      ; DE0_NANO           ; DE0_NANO           ;
; Family name                                                                ; Cyclone IV E       ; Cyclone IV GX      ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
; Parallel Synthesis                                                         ; On                 ; On                 ;
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Optimization Technique                                                     ; Balanced           ; Balanced           ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;
; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Strict RAM Replacement                                                     ; Off                ; Off                ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
; Report Parameter Settings                                                  ; On                 ; On                 ;
; Report Source Assignments                                                  ; On                 ; On                 ;
; Report Connectivity Checks                                                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization During Synthesis                              ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; SDC constraint protection                                                  ; Off                ; Off                ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
; Synthesis Seed                                                             ; 1                  ; 1                  ;
+----------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processors 2-4         ;   0.0%      ;
+----------------------------+-------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                                            ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                                                                              ; Library ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------------------------------+---------+
; VGA_DRIVER.v                     ; yes             ; User Verilog HDL File  ; C:/Users/JoshyD/Documents/School/Research/Summer 2018/CV-with-FPGA/Lab3_FPGA_Template/VGA_DRIVER.v        ;         ;
; DE0_NANO.v                       ; yes             ; User Verilog HDL File  ; C:/Users/JoshyD/Documents/School/Research/Summer 2018/CV-with-FPGA/Lab3_FPGA_Template/DE0_NANO.v          ;         ;
; Dual_Port_RAM_M9K.v              ; yes             ; User Verilog HDL File  ; C:/Users/JoshyD/Documents/School/Research/Summer 2018/CV-with-FPGA/Lab3_FPGA_Template/Dual_Port_RAM_M9K.v ;         ;
; IMAGE_PROCESSOR.v                ; yes             ; User Verilog HDL File  ; C:/Users/JoshyD/Documents/School/Research/Summer 2018/CV-with-FPGA/Lab3_FPGA_Template/IMAGE_PROCESSOR.v   ;         ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------------------------------+---------+


+--------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary            ;
+---------------------------------------------+----------+
; Resource                                    ; Usage    ;
+---------------------------------------------+----------+
;                                             ;          ;
; Total combinational functions               ; 0        ;
; Logic element usage by number of LUT inputs ;          ;
;     -- 4 input functions                    ; 0        ;
;     -- 3 input functions                    ; 0        ;
;     -- <=2 input functions                  ; 0        ;
;                                             ;          ;
; Logic elements by mode                      ;          ;
;     -- normal mode                          ; 0        ;
;     -- arithmetic mode                      ; 0        ;
;                                             ;          ;
; Total registers                             ; 0        ;
;     -- Dedicated logic registers            ; 0        ;
;     -- I/O registers                        ; 0        ;
;                                             ;          ;
; I/O pins                                    ; 71       ;
;                                             ;          ;
; Embedded Multiplier 9-bit elements          ; 0        ;
;                                             ;          ;
; Maximum fan-out node                        ; CLOCK_50 ;
; Maximum fan-out                             ; 1        ;
; Total fan-out                               ; 71       ;
; Average fan-out                             ; 0.50     ;
+---------------------------------------------+----------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |DE0_NANO                  ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 71   ; 0            ; |DE0_NANO           ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                            ;
+----------------------------------------+--------------------------------------+
; Register name                          ; Reason for Removal                   ;
+----------------------------------------+--------------------------------------+
; VGA_DRIVER:driver|line_count[0..9]     ; Stuck at GND due to stuck port clock ;
; VGA_DRIVER:driver|pixel_count[0..9]    ; Stuck at GND due to stuck port clock ;
; Total Number of Removed Registers = 20 ;                                      ;
+----------------------------------------+--------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------+
; Port Connectivity Checks: "VGA_DRIVER:driver"                    ;
+----------------------+-------+----------+------------------------+
; Port                 ; Type  ; Severity ; Details                ;
+----------------------+-------+----------+------------------------+
; CLOCK                ; Input ; Info     ; Explicitly unconnected ;
; PIXEL_COLOR_IN[7..2] ; Input ; Info     ; Stuck at GND           ;
+----------------------+-------+----------+------------------------+


+-----------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "Dual_Port_RAM_M9K:mem"                                                                     ;
+-------------+--------+----------+-------------------------------------------------------------------------------------+
; Port        ; Type   ; Severity ; Details                                                                             ;
+-------------+--------+----------+-------------------------------------------------------------------------------------+
; input_data  ; Input  ; Info     ; Explicitly unconnected                                                              ;
; clk_W       ; Input  ; Info     ; Explicitly unconnected                                                              ;
; clk_R       ; Input  ; Info     ; Explicitly unconnected                                                              ;
; output_data ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type                  ; Count                       ;
+-----------------------+-----------------------------+
; boundary_port         ; 71                          ;
; cycloneiii_lcell_comb ; 2                           ;
;     normal            ; 2                           ;
;         0 data inputs ; 2                           ;
;                       ;                             ;
; Max LUT depth         ; 0.00                        ;
; Average LUT depth     ; 0.00                        ;
+-----------------------+-----------------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:00     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
    Info: Version 15.0.0 Build 145 04/22/2015 Patches 0.01we SJ Web Edition
    Info: Processing started: Wed Aug 15 18:18:32 2018
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE0_NANO -c DE0_NANO
Warning (125092): Tcl Script File DE_NANO_SOPC.qip not found
    Info (125063): set_global_assignment -name QIP_FILE DE_NANO_SOPC.qip
Warning (125092): Tcl Script File myfirstpll.qip not found
    Info (125063): set_global_assignment -name QIP_FILE myfirstpll.qip
Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.
Info (12021): Found 1 design units, including 1 entities, in source file vga_driver.v
    Info (12023): Found entity 1: VGA_DRIVER
Info (12021): Found 1 design units, including 1 entities, in source file de0_nano.v
    Info (12023): Found entity 1: DE0_NANO
Info (12021): Found 1 design units, including 1 entities, in source file dual_port_ram_m9k.v
    Info (12023): Found entity 1: Dual_Port_RAM_M9K
Info (12021): Found 1 design units, including 1 entities, in source file image_processor.v
    Info (12023): Found entity 1: IMAGE_PROCESSOR
Info (12021): Found 1 design units, including 1 entities, in source file pll.v
    Info (12023): Found entity 1: PLL
Info (12127): Elaborating entity "DE0_NANO" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at DE0_NANO.v(98): truncated value with size 32 to match size of target (15)
Warning (10030): Net "VGA_COLOR_IN" at DE0_NANO.v(35) has no driver or initial value, using a default initial value '0'
Warning (10034): Output port "GPIO_0_D[33..24]" at DE0_NANO.v(26) has no driver
Warning (10034): Output port "GPIO_0_D[22]" at DE0_NANO.v(26) has no driver
Warning (10034): Output port "GPIO_0_D[20]" at DE0_NANO.v(26) has no driver
Warning (10034): Output port "GPIO_0_D[18]" at DE0_NANO.v(26) has no driver
Warning (10034): Output port "GPIO_0_D[16]" at DE0_NANO.v(26) has no driver
Warning (10034): Output port "GPIO_0_D[14]" at DE0_NANO.v(26) has no driver
Warning (10034): Output port "GPIO_0_D[12]" at DE0_NANO.v(26) has no driver
Warning (10034): Output port "GPIO_0_D[10]" at DE0_NANO.v(26) has no driver
Warning (10034): Output port "GPIO_0_D[8]" at DE0_NANO.v(26) has no driver
Warning (10034): Output port "GPIO_0_D[6]" at DE0_NANO.v(26) has no driver
Warning (10034): Output port "GPIO_0_D[4..0]" at DE0_NANO.v(26) has no driver
Info (12128): Elaborating entity "Dual_Port_RAM_M9K" for hierarchy "Dual_Port_RAM_M9K:mem"
Warning (10036): Verilog HDL or VHDL warning at Dual_Port_RAM_M9K.v(34): object "r_addr_reg" assigned a value but never read
Info (12128): Elaborating entity "VGA_DRIVER" for hierarchy "VGA_DRIVER:driver"
Info (12128): Elaborating entity "IMAGE_PROCESSOR" for hierarchy "IMAGE_PROCESSOR:proc"
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "GPIO_0_D[0]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[1]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[2]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[3]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[4]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[5]" is stuck at VCC
    Warning (13410): Pin "GPIO_0_D[6]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[7]" is stuck at VCC
    Warning (13410): Pin "GPIO_0_D[8]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[9]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[10]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[11]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[12]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[13]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[14]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[15]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[16]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[17]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[18]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[19]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[20]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[21]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[22]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[23]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[24]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[25]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[26]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[27]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[28]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[29]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[30]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[31]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[32]" is stuck at GND
    Warning (13410): Pin "GPIO_0_D[33]" is stuck at GND
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 37 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "CLOCK_50"
    Warning (15610): No output dependent on input pin "GPIO_1_D[0]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[1]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[2]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[3]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[4]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[5]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[6]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[7]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[8]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[9]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[10]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[11]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[12]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[13]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[14]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[15]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[16]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[17]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[18]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[19]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[20]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[21]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[22]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[23]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[24]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[25]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[26]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[27]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[28]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[29]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[30]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[31]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[32]"
    Warning (15610): No output dependent on input pin "GPIO_1_D[33]"
    Warning (15610): No output dependent on input pin "KEY[0]"
    Warning (15610): No output dependent on input pin "KEY[1]"
Info (21057): Implemented 71 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 37 input pins
    Info (21059): Implemented 34 output pins
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 89 warnings
    Info: Peak virtual memory: 4822 megabytes
    Info: Processing ended: Wed Aug 15 18:18:44 2018
    Info: Elapsed time: 00:00:12
    Info: Total CPU time (on all processors): 00:00:28


